View MSM5416258A_32887.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

E2L0047-28-Z2 Semiconductor
Semiconductor MSM5416258A
DESCRIPTION
This version: Dec. 1998 MSM5416258A Previous version: Jan. 1998
262,144-Word 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
The MSM5416258A is a 262,144-word 16-bit dynamic RAM fabricated in Oki's CMOS silicon gate technology. The MSM5416258A achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM5416258A is available in a 44/40-pin plastic TSOP.
FEATURES
* 262,144-word 16-bit configuration * Single 5.0 V power supply, 0.5 V tolerance * Input: TTL compatible * Output: TTL compatible, 3-state * Refresh: 512 cycles/8 ms * Fast page mode with EDO, read modify write capability * Byte wide control: 2 CAS control * CAS before RAS refresh, hidden refresh, RAS only refresh capability * Package : 44/40-pin 400 mil plastic TSOP (Type II) (TSOPII44/40-P-400-0.80-K) (Product : MSM5416258A-xxTS-K) xx indicates speed rank.
PRODUCT FAMILY
Family MSM5416258A-40 MSM5416258A-45 Access Time (Max.) tRAC tAA tCAC tOEA 40 ns 22 ns 10 ns 10 ns 45 ns 24 ns 12 ns 12 ns Cycle Time (Min.) tRC 80 ns 90 ns tHPC 15 ns 20 ns Power Dissipation (Max.) 825 mW 770 mW
1/21
Semiconductor
MSM5416258A
PIN CONFIGURATION (TOP VIEW)
VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 1 2 3 4 5 6 7 8 9 10 VSS* NC WE RAS NC A0 A1 A2 A3 VCC 13 14 15 16 17 18 19 20 21 22 44/40-Pin Plastic TSOP (II) (K Type)
Pin Name A0 - A8 RAS LCAS, UCAS DQ0 - DQ15 WE OE VCC VSS NC VSS* Address Input Write Enable Output Enable Ground (0 V) No Connection Ground (0 V)*
44 43 42 41 40 39 38 37 36 35 32 31 30 29 28 27 26 25 24 23
VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 VSS* LCAS UCAS OE A8 A7 A6 A5 A4 VSS
Function Row Address Strobe Column Address Strobe Data - Input / Data - Output
Power Supply (5.0 V)
Note: The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. *: For improved signal integrity, it is recommended to connect the VSS* pins, pin 13 and pin 32, to GND: the pins are electrically connected to internal GND. 2/21
Semiconductor
MSM5416258A
BLOCK DIAGRAM
OE RAS LCAS UCAS
Timing Generator
WE
I/O Controller I/O Controller 8 Output Buffers 8
DQ0 - DQ7
9 Column Address Buffers Internal Address Counter Row Address Buffers 9 Column Decoders 8 I/O Selector 16 Input Buffers Input Buffers 8
A0 - A8
Refresh Control Clock
Sense Amplifiers
16
8 9 9 Row Decoders Word Drivers Memory Cells 8
8
DQ8 - DQ15
Output Buffers 8
VCC
On-chip VBB Generator
VSS
FUNCTION TABLE
Input Pin RAS H L L L L L L L L LCAS * H L H L L H L L UCAS * H H L L H L L L WE * * H H H L L L H OE * * L L L H H H H High-Z High-Z DOUT High-Z DOUT DIN Don't Care DIN High-Z DQ Pin DQ0 - DQ7 DQ8 - DQ15 High-Z High-Z High-Z DOUT DOUT Don't Care DIN DIN High-Z Function Mode Standby Refresh Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write --
* : "H" or "L"
3/21
Semiconductor
MSM5416258A
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Voltage on Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VT IOS PD Topr Tstg Condition Ta = 25C Ta = 25C Ta = 25C -- -- Rating -1.0 to 7.0 50 1 0 to 70 -55 to 150 Unit V mA W C C
Recommended Operating Conditions
Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 4.5 0 2.4 -1.0 Typ. 5.0 0 -- -- Max. 5.5 0
(Ta = 0C to 70C) Unit V V V V
VCC + 1.0 0.8
Capacitance
Parameter Input Capacitance (A0 - A8) Input Capacitance (RAS, LCAS, UCAS, WE, OE) Input / Output Capacitance (DQ0 - DQ15) Symbol CIN1 CIN2 CI/O Typ. -- -- --
(VCC = 5.0 V 0.5 V, Ta = 25C, f = 1 MHz) Max. 5 7 7 Unit pF pF pF
4/21
Semiconductor DC Characteristics
MSM5416258A
(VCC = 5.0 V 0.5 V, Ta = 0C to 70C) Parameter Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS Only Refresh) Average Power Supply Current (Fast Page Mode) Average Power Supply Current (CAS before RAS Refresh) Symbol VOH VOL ILI ILO Condition IOH = -2.5 mA IOL = 2.0 mA 0 V VI VCC DQi Disable 0 V VO 5.5 V RAS, CAS Cycling, tRC = Min. RAS, CAS = VIH RAS = Cycling, CAS = VIH, tRC = Min. RAS = VIL, CAS Cycling, tHPC = Min. RAS = Cycling, CAS before RAS MSM5416258A -40 Min. 2.4 0 -10 -10 Max. VCC 0.4 10 10 MSM5416258A -45 Min. 2.4 0 -10 -10 Max. VCC 0.4 10 10 V V mA mA Unit Note
ICC1
--
150
--
140
mA 1, 2
ICC2
--
3
--
3
mA
1
ICC3
--
150
--
140
mA 1, 2
ICC4
--
130
--
115
mA 1, 3
ICC5
--
150
--
140
mA 1, 2
Notes : 1. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while RAS = VIL. 3. The address can be changed once or less while CAS = VIH.
5/21
Semiconductor AC Characteristics (1/2)
Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time
Fast Page Mode Read Modify Write Cycle Time
MSM5416258A
(VCC = 5.0 V 0.5 V, Ta = 0C to 70C)
Symbol
MSM5416258A -40 Min. Max. -- -- -- -- 40 10 22 10 22 -- -- 8 8 8 8 35 8 -- 10,000 100,000 -- -- -- 10,000 -- -- -- 30 18 -- -- -- -- -- -- 80 115 15 55 -- -- -- -- -- 0 3 3 3 1.5 3 2 -- 30 40 40 8 8 5 6 35 5 22 18 13 0 8 0 6 30 22
MSM5416258A -45 Min. 90 130 20 60 -- -- -- -- -- 0 3 3 3 1.5 3 2 -- 35 45 45 10 8 6 7 35 5 24 18 13 0 8 0 6 30 24 Max. -- -- -- -- 45 12 24 12 24 -- -- 8 8 8 8 35 8 -- 10,000 100,000 -- -- -- 10,000 -- -- -- 30 18 -- -- -- -- -- --
Unit Note ns ns ns ns ns 7, 12, 13 ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 12 13 17 8 8 8 8 7, 12 7, 12 7, 13
tRC tRWC tHPC tPRWC tRAC tCAC tAA tOEA tCPA tCLZ tCOH tOFF tOEZ tREZ tWEZ tT tREF tRP tRAS tRASP tRSH tROH tCP tCAS tCSH tCRP tRHCP tRCD tRAD tASR tRAH tASC tCAH tAR tRAL
Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from OE Access Time from CAS Precharge Output Low Impedance Time from CAS Data Hold After CAS Low Output Buffer Turn-off Delay Time Output Buffer Turn-off Delay Time from OE Output Buffer Turn-off Delay Time from RAS Output Buffer Turn-off Delay Time from WE Transition Time Refresh Period RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode) RAS Hold Time RAS Hold Time Reference to OE CAS Precharge Time CAS Pulse Width CAS Hold Time CAS to RAS Precharge Time RAS Hold Time from CAS Precharge RAS to CAS Delay Time RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address Hold Time from RAS Column Address to RAS Lead Time
6/21
Semiconductor AC Characteristics (2/2)
Parameter Read Command Set-up Time Read Command Hold Time Read Command Hold Time Reference to RAS WE Pulse Width (DQ Disable) Write Command Set-up Time Write Command Hold Time Write Command Pulse Width Write Command Hold Time from RAS OE Command Hold Time Write Command to CAS Lead Time Write Command to RAS Lead Time Data to CAS Delay Time Data to OE Delay Time Data-in Set-up Time Data-in Hold Time Data-in Hold Time referenced to RAS OE to Data-in Delay Time OE "L" to CAS "H" Lead Time CAS "H" to OE "L" Lead Time Hi-Z Command Pulse Width CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time CAS Active Delay Time from RAS Precharge RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) MSM5416258A -40 Min. tRCS tRCH tRRH tWEP tWCS tWCH tWP tWCR tOEH tCWL tRWL tDZC tDZO tDS tDH tDHR tOED tOCH tCHO tOEP tCWD tAWD tRWD tRPC tCSR tCHR 0 0 0 10 0 6 6 30 6 6 8 0 0 0 6 30 8 10 10 10 22 32 50 0 10 10 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
MSM5416258A
(VCC = 5.0 V 0.5 V, Ta = 0C to 70C)
Symbol
MSM5416258A -45 Min. 0 0 0 10 0 6 6 30 7 7 9 0 0 0 7 30 8 10 10 10 22 32 55 0 10 10 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 11 11 11 10 10 11 9 9
7/21
Semiconductor
MSM5416258A
Notes:
1. All voltages are referenced to VSS. 2. This parameter is dependent upon the cycle rate. 3. This parameter is dependent upon the output loading. Specified values are obtained with the output open. 4. An initial pause of 200 ms is required after power-up, followed by any 8 RAS cycles. (Example : RAS-only-refresh) before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS before RAS cycles instead of 8 RAS cycles are required. 5. The AC characteristics assume tT = 5 ns. 6. VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 7. Data outputs are measured with a load of 50 pF. DOUT reference levels: VOH/VOL = 2.0 V/1.4 V. Note that VOL is defined as 1.4 V when VSS* pins, pin 13 and pin 32, were open. The data output measurements under VOH/VOL = 2.0 V/0.8 V are guaranteed when VSS* pins, pin 13 and pin 32, were connected to GND. 8. tREZ (Max.), tOFF (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the outputs achieve the open circuit condition and are not referenced to output voltage levels. This parameter is sampled and not 100% tested. 9. Either tRCH or tRRH must be satisfied for a read cycle. 10. These parameters are referenced to CAS leading edge of early write cycles and to WE leading edge in OE-controlled write cycles and read-modify-write cycles. 11. tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (Min.), the cycle is an early write cycle and the data out pins will remain open circuit throughout the entire cycle. If tRWD tRWD (Min.), tCWD tCWD (Min.) and tAWD tAWD (Min.), the cycle is a read-modify-write cycle and the data out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data out is indeterminate. 12. Operation within the tRCD (Max.) limit insures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then access time is controlled by tCAC. 13. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (Max.) limit, then access time is controlled by tAA. 14. Input levels at the AC testing are 3.0 V/0 V. 15. Addresses (A0 - A8) may be changed two times or less while RAS = VIL. 16. Addresses (A0 - A8) may be changed once or less while CAS = VIH and RAS = VIL. 17. This is guaranteed by design. (tCOH = tCAC - output transition time). This parameter is not 100% tested. 18. This parameter is dependent upon the number of address transitions. Specified values are measured with a maximum of two transitions per address cycle in Fast Page Mode.
8/21
Semiconductor
MSM5416258A
TIMING WAVEFORM
Read Cycle (RAS Output Control)
RAS
UCAS LCAS
A0 - A8
WE
OE
DQ0 - 7
DQ8 - 15
,, ,
tRC tRAS tRP tCRP tCSH tRCD tRSH tCAS tAR tRAD tRAL tASR tRAH tASC tCAH Row Column tRCS tRCH tROH tRRH tOEA tOEZ tCAC tAA tOFF High-Z Valid Data tRAC tOFF High-Z Valid Data "H" or "L"
9/21
Semiconductor
Read Cycle (CAS Output Control)
RAS
UCAS LCAS
A0 - A8
WE
OE
DQ0 - 7
DQ8 - 15
,, ,
tRC tRAS tRP tCRP tCSH tRCD tRSH tCAS tAR tRAD tRAL tASR tRAH tASC tCAH Row Column tRCS tRRH tROH tOEA tOEZ tCAC tOFF tAA High-Z Valid Data tRAC High-Z Valid Data "H" or "L"
MSM5416258A
10/21
Semiconductor
Early Write Cycle (LCAS and UCAS Active)
RAS
UCAS LCAS
A0 - A8
WE
OE
DQ0 - 7
DQ8 - 15
,, , ,, ,
tRC tRAS tRP tCRP tCSH tRCD tRSH tCAS tAR tRAD tRAL tASR tRAH tASC tCAH Row Column tCWL tRWL tWP tWCR tWCS tWCH tDHR tDS tDH Valid Data tDS tDH Valid Data "H" or "L"
MSM5416258A
11/21
Semiconductor
Late Write Cycle (LCAS and UCAS Active)
RAS
UCAS LCAS
A0 - A8
WE
OE
DQ0 - 7
DQ8 - 15
,, , ,, ,,
tRC tRAS tRP tCRP tCSH tRCD tRSH tCAS tAR tRAD tRAL tASR tRAH tASC tCAH Row Column tRCS tCWL tRWL tWP tWCR tOEH tDS tDH Valid Data tDS tDH Valid Data "H" or "L"
MSM5416258A
12/21
Semiconductor
Read Modify Write Cycle (LCAS and UCAS Active)
RAS
UCAS LCAS
A0 - A8
WE
OE
DQ0 - 7
DQ8 - 15
,, , ,, ,
tRWC tRAS tRP tCRP tCSH tRCD tRSH tCAS tAR tRAD tRAL tASR tRAH tASC tCAH Row Column tAWD tRCS tCWL tRWL tWP tRWD tDZO tCWD tOEA tOEZ tOEH tOED tDS tCAC tDZC tDH Out In tRAC tDS tDH Out In "H" or "L"
MSM5416258A
13/21
Semiconductor Fast Page Mode Read Cycle
MSM5416258A
tRASP tAR RAS tRHCP tRP
, , ,
tCRP tRCD tCP tCP UCAS LCAS tCAS tCAS tCAS tRAD tASR tRAH tASC tCSH tCAH tASC tCAH tASC tRAL tCAH A0 - A8 Row Column Column tRCS Column tRCS tRCS tRCH tRCH tRCH WE tAA tAA tAA tOEA tCPA tOEA tCAC tCPA tOEA tCAC tRRH OE tCAC tOFF tOFF tOFF tRAC tOEZ tOEZ tOEZ DQ0 - 7 High-Z Valid Data Valid Data Valid Data tCLZ tCLZ tCLZ DQ8 - 15 High-Z Valid Data Valid Data Valid Data "H" or "L"
tPC
tRSH
tCRP
14/21
Semiconductor
Fast Page Mode Read High-Z Operation
tRC tRASP RAS tAR tRP
tCSH tCRP tRCD tCP UCAS LCAS tCAS tRAD tASR tRAH Row tASC tCAH A0 - A8 Column tRCS WE tRAC tOEA OE tAA tCAC tAA DQ0 - 7
High-Z Valid Data
tHPC tCP tCAS tCP tCAS
tRSH tCRP tCAS tRAL tASC tCAH Column tASC tCAH Column
,
tASC tCAH Column tRRH tRCH tRCS tRCH tCHO tOCH tWEP tCAC tOEP tOEP tCAC tCPA tAA tCAC tDOH tOEZ tOEA tOEZ tOEA tWEZ tAA tREZ
Valid Data Valid Data Valid Data Valid Data
MSM5416258A
DQ8 - 15
High-Z
Valid Data
Valid Data
Valid Data
Valid Data
Valid Data
15/21
"H" or "L"
Semiconductor
Fast Page Mode Early Write Cycle
RAS
UCAS LCAS
A0 - A8
WE
OE
DQ0 - 7
DQ8 - 15
, , ,, , , , ,
MSM5416258A
tRC tRASP tRP tCRP tCSH tPC tRCD tCP tCP tRSH tCAS tCAS tCAS tAR tRAD tCAH tRAL tASR tRAH tASC tASC tCAH tASC tCAH Row Column Column Column tCWL tCWL tCWL tWCS tWP tWCH tWCS tWP tWCH tWCS tWP tWCH tDS tDH tDS tDH tDS tDH
Input Data
Input Data tDS
Input Data tDS
tDS
tDH
tDH
tDH
Input Data
Input Data
Input Data
"H" or "L"
16/21
Semiconductor Fast Page Mode Read Modify Write Cycle
MSM5416258A
,, ,
tRC tRASP tRP RAS tCSH tCRP tRCD tCAS tCP tPRWC tCAS tCP tRSH tCAS UCAS LCAS tAR tRAD tRAL tASR tRAH Row tASC tCAH tASC tCAH tASC tCAH A0 - A8 Column tAWD Column tAWD Column tAWD tCWL tCWL tCWL WE tCWD tCWD tCWD tRCS tWP tWP tWP tOEA tOEZ tOEA tOEZ tOEA tOEZ OE tCAC tCAC tCAC tAA tDH tAA tDH tAA tDH tDS tDS tDS DQ0 - 7
Out In Out In Out In
tCAC tAA
tDH
tDS
tCAC tDS tAA
Out
tDH
tDH tCAC tDS tAA
Out In
DQ8 - 15
Out
In
In
"H" or "L"
17/21
Semiconductor
CAS before RAS Refresh Cycle
RAS
UCAS LCAS
A0 - A8
WE
OE
DQ0 - 7
DQ8 - 15
,,,, ,
MSM5416258A
tRC tRP tRAS tRP tRPC tCSR tCHR tRPC
Inhibit Falling Transition
tOFF
High-Z
tOFF
High-Z
"H" or "L"
18/21
Semiconductor
Hidden Refresh Cycle
RAS
UCAS LCAS
A0 - A8
WE
OE
DQ0 - 7
DQ8 - 15
,, ,
tRC tRAS tRP tRAS tCRP tRCD tRSH tCHR tAR tRAD tRAL tASR tRAH tASC tCAH Row Column tRCS tRRH tROH tOEA tOEZ tRAC tCAC tOFF tAA
High-Z
MSM5416258A
Valid Data
tRAC
tCAC tAA
tOFF
High-Z
Valid Data
"H" or "L"
19/21
Semiconductor
RAS Only Refresh Cycle
RAS
UCAS LCAS
A0 - A8
WE
OE
DQ0 - 7 DQ8 - 15
, ,,,,
MSM5416258A
tRC tRAS tRP tCRP tRPC tASR tRAH Row
High-Z High-Z
"H" or "L"
20/21
Semiconductor
MSM5416258A
PACKAGE DIMENSIONS
(Unit : mm)
TSOPII44/40-P-400-0.80-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.49 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
21/21
E2Y0002-28-41
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents cotained herein may be reprinted or reproduced without our prior permission. MS-DOS is a registered trademark of Microsoft Corporation.
2.
3.
4.
5.
6.
7.
8.
9.
Copyright 1998 Oki Electric Industry Co., Ltd.
Printed in Japan

▲Up To Search▲

Price & Availability of MSM5416258A

	To Download MSM5416258A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .